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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES 14-Bit, 65MSPS ADC Low Power: 590mW at 65MSPS with Fin to Nyquist 340mW at 40MSPS with Fin to Nyquist On-Chip Reference and Sample/Hold 750MHz Analog Input Bandwidth SNR = 74dB up to Nyquist SFDR = 83dB up to Nyquist Differential Non Linearity Error = 0.6LSB Guaranteed No Missing Codes Over Full Temp range 1V to 2V p-p Differential Full Scale Analog Input Range Single +5.0V Analog Supply, 3/5V Driver Supply Out-of-Range Indicator Straight Binary or Two's Complement Output Data 48-Lead LQFP Package APPLICATIONS Communications Subsystems (Microcell, Picocell) Medical and High End Imaging Equipment Ultrasound Equipment
14-Bit, 40/65 MSPS Monolithic A/D Converter AD9244
FUNCTIONAL BLOCK DIAGRAM
AVDD REFT REFB DRVDD
AD9244
VIN+ SHA VINCLK+ CLKDUTY REFERENCE TIMING
EIGHT STAGE PIPELINE ADC
OUTPUT REGISTER
DFS
14
OTR
DB13-DB0 14 OEB
AGND CML VR VREF REF REF SENSE GND
DRGND
PRODUCT DESCRIPTION The AD9244 is a monolithic, single 5V supply, 14-bit, 65MSPS Analog to Digital Converter with an on-chip, high performance sample and hold amplifier and voltage reference. The AD9244 uses a multi-stage differential pipelined architecture with output error correction logic to provide 14-bit accuracy at 65MSPS data rates and guarantees no missing codes over the full operating temperature range. The AD9244 has an on-board, programmable voltage reference. An external reference can also be chosen to suit the DC accuracy and temperature drift requirements of the application. A differential clock input is used to control all internal conversion cycles. The digital output data can be presented in straight binary or in two's complement format. An out of range (OTR) signal indicates an overflow condition, which can be used with the most significant bit to determine low or high overflow. Fabricated on an advanced CMOS process, the AD9244 is available in a 48 pin surface mount plastic package (48 LQFP) and is specified for operation over the industrial temperature range of (-40C to +85C).
PRODUCT HIGHLIGHTS Low Power--The AD9244 at 590mW consumes a fraction of the power of presently available in existing, high speed monolithic solutions. On-Board Sample-and-Hold (SHA)--The versatile SHA input can be configured for either single-ended or differential inputs. Out of Range (OTR)--The OTR output bit indicates when the input signal is beyond the AD9244's input range. Single Supply--The AD9244 uses a single +5V power supply simplifying system power supply design. It also features a separate digital output driver supply line to accommodate 3V and 5V logic families. IF Sampling--The AD9244 delivers outstanding performance at input frequencies beyond the first Nyquist zone. Sampling at 65MSPS, with an input frequency of 100MHz, the AD9244 delivers 70dB SNR and SFDR of 82dB.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 020629106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
AD9244-SPECIFICATIONS
DC SPECIFICATIONS (AVDD = +5 V, CLKVDD=3V, DRVDD = +3.0 V, fSAMPLE = 65 MSPS (-65) or 40MSPS (-40), INPUT RANGE = 2V p-p, DIFFERENTIAL ANALOG
INPUTS, DIFFERENTIAL CLOCK INPUTS, EXTERNAL REFERENCE, TMIN to TMAX unless otherwise noted)
Parameter RESOLUTION DC ACCURACY No Missing Codes Guaranteed Offset Error Gain Error1 Differential Nonlinearity (DNL)2 Integral Nonlinearity (INL)2 TEMPERATURE DRIFT Offset Error Gain Error1 INTERNAL VOLTAGE REFERENCE Output Voltage Error (2V VREF) Load Regulation @ 1ma Output Voltage Error (1V VREF) Load Regulation @ 0.5ma INPUT REFERRED NOISE VREF=2V VREF=1V ANALOG INPUT Input Voltage Range (differential) VREF=2V VREF=1V Common Mode Voltage Input Capacitance3 Input Bias Current Analog Bandwidth (full power) REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltages AVDD DRVDD Supply Current IAVDD2 IDRVDD2 POWER CONSUMPTION DC Input4 Sinewave Input2 Temp Full Full Full Full Full +25C Full +25C Full Full Full Full Full Full +25C +25C Test Level VI VI VI VI IV I IV I V V VI V V V V V 3.9 2.79 3.9 2.79 AD9244BST-65 Min Typ Max 14 14 AD9244BST-40 Min Typ Max 14 14 Units bits bits %FSR %FSR LSB LSB LSB LSB ppm/C ppm/C mV mV
0.6 1.9
0.6 1.3
0.82
0.79
LSB rms LSB rms
+25C +25C Full +25C +25C +25C Full
V V V IV IV V V
2 1 0.5 7 5 750 5 2 0.5
2 1 2 7 5 750 5
V p-p V p-p V pF mA MHz k
Full Full Full +25C Full +25C Full Full
IV IV IV I IV I V VI
4.75 5.0 2.7 3.0 104 12
5.25 3.6
4.75 5.0 2.7 3.0 62 7.6
5.25 3.6
V V mA mA
590
340
mW mW
NOTES 1 Gain Error is based on the ADC only (with a fixed 1.0V external reference). 2 Measured at maximum clock rate, fIN = 2.4MHz, full scale sinewave, with approximately 5pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 2 for the equivalent analog input structure. 4 Measured with dc input at maximum clock rate. Specifications subject to change without notice
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PRELIMINARY TECHNICAL DATA
AD9244-SPECIFICATIONS
AC SPECIFICATIONS (AVDD = +5 V, CLKVDD=3V, DRVDD = +3.0 V, fSAMPLE = 65 MSPS (-65) or 40MSPS (-40), INPUT RANGE = 2V p-p, DIFFERENTIAL ANALOG
INPUTS, DIFFERENTIAL CLOCK INPUTS, EXTERNAL REFERENCE, TMIN to TMAX unless otherwise noted)
Parameter SIGNAL TO NOISE RATIO fIN = 2.4 MHz Temp Full +25C +25C +25C +25C Test Level VI I V V V AD9244BST-65 Min Typ Max AD9244BST-40 Min Typ Max Units
75 74 74 70
75 75 71
dBc dBc dBc dBc
fIN = 20 MHz fIN = 35 MHz fIN = 100 MHz SIGNAL TO NOISE AND DISTORTION (SINAD) fIN = 2.4 MHz
Full +25C +25C +25C +25C Full +25C +25C +25C +25C Full Full Full Full Full +25C +25C +25C +25C
VI I V V V VI I V V V V V V V VI I V V V
74 72 73 70
75 74 70
dBc dBc dBc dBc
fIN = 20 MHz fIN = 35 MHz fIN = 100 MHz TOTAL HARMONIC DISTORTION fIN = 2.4 MHz
-87 -82 -82 -80 -90 -83 -83 -82
-92 -82 -74 -97 -79 -77
dBc dBc dBc dBc
fIN = 20 MHz fIN = 35 MHz fIN = 100 MHz WORST OF 2nd, 3rd HARMONIC fIN = 2.5 MHz fIN = 20 MHz fIN = 35 MHz fIN = 100 MHz SPURIOUS FREE DYNAMIC RANGE fIN = 2.4 MHz
89 83 83 82
95 82 79
dBc dBc dBc dBc
fIN = 20 MHz fIN = 35 MHz fIN = 100 MHz
Specifications subject to change without notice
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PRELIMINARY TECHNICAL DATA
DIGITAL SPECIFICATIONS (AVDD = +5 V, DRVDD = +3.0V, fSAMPLE = 65 MSPS, VREF = 2V, EXTERNAL REFERENCE, TMIN to TMAX unless otherwise noted)
Parameter DIGITAL INPUTS (CLK+,CLK-, DFS, DUTY and OEB) Logic "1" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current Input Capacitance DIGITAL OUTPUTS (DRVDD=5V) Logic "1" Voltage (IOH=50a) Logic "1" Voltage (IOH=0.5ma) Logic "0" Voltage (IOL=1.6ma) Logic "0" Voltage (IOL=50a)
1
AD9244-SPECIFICATIONS
Temp
Test Level
AD9244BST-65 Min Typ Max
AD9244BST-40 Min Typ Max
Units
Full Full Full Full +25C Full Full Full Full Full Full Full Full +25C
IV IV IV IV V IV IV IV IV IV IV IV IV V
+2.0 +0.8 10 10 5 4.5 2.4 0.4 0.1 2.95 2.80 0.4 0.05 5
+2.0 +0.8 10 10 5 4.5 2.4 0.4 0.1 2.95 2.80 0.4 0.05 5
V V a a pf V V V V V V V V pf
DIGITAL OUTPUTS (DRVDD=3V)1 Logic "1" Voltage (IOH=50a) Logic "1" Voltage (IOH=0.5ma) Logic "0" Voltage (IOL=50a) Logic "0" Voltage (IOL=0.5ma) Output Capacitance
NOTES 1. Output Voltage Levels measured with 5pF load on each output Specifications subject to change without notice
SWITCHING SPECIFICATIONS (AVDD = +5 V, DRVDD = +3.0V, TMIN to TMAX unless otherwise noted)
Parameter CLOCK INPUT PARAMETERS Max Conversion Rate Min Conversion Rate Clock Period1 Clock Pulsewidth High2 Clock Pulsewidth Low2 DATA OUTPUT PARAMETERS Output Delay (tOD)3 Pipeline Delay (Latency) Aperature Delay (tA) Aperature Uncertainty (Jitter) Wake-Up Time3 OUT OF RANGE RECOVERY TIME
NOTES
1 2 3 4
Temp Full Full Full Full Full Full Full Full Full Full Full
Test Level VI V V V V V V V V V V
AD9244BST-65 Min Typ Max 65 500 15.4 6.2 6.2 3.5 8 3 0.5 2.5 2 7
AD9244BST-40 Min Typ Max 40 500 25 8.8 8.8 3.5 8 3 0.5 2.5 1 7
Units MHz kHz ns ns ns ns Clock Cycles ns ps rms ms Clock Cycles
The clock period may be extended to 2s with no degradation in specified performance at +25C. For the AD9244-65 only, with duty cycle stabilizer enabled. DCS function not applicable for -40 model. Output delay is measured from clock 50% transition to data 50% transition, with 5pF load on each output.
Wake-up time is dependent on value of decoupling capacitors, typical values shown with 0.1F and 10F capacitors on REFT and REFB. Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA
AD9244-SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS*
Pin Name AVDD DRVDD AGND AVDD REFGND CLK, DUTY DFS VIN+, VINVREF REFSENSE REFB, REFT CM LEVEL VR OTR BIT0-BIT13 OEB
WRT AGND DRGND DRGND DRVDD AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND DRGND DRGND
Min -0.3 -0.3 -0.3 -6.5 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3
Max +6.5 +6.5 +0.3 +6.5 +0.3 AVDD+0.3 AVDD+0.3 AVDD+0.3 AVDD+0.3 AVDD+0.3 AVDD +0.3 AVDD+0.3 AVDD+0.3 AVDD+0.3 DRVDD+0.3 DRVDD+0.3 20 +150 +175 +175 +300
Units V V V V V V V V V V V V V V V V mA C C C C
EXPLANATIONOFTESTLEVELS TestLevel I 100% production tested II 100% production tested at 25C and sample tested at specified temperatures III Sample tested only IV Parameter is guaranteed by design and characterization testing V Parameter is a typical value only VI 100% production tested at 25C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.
Digital Output Current Storage Temperature Operating Temperature Case Temperature Lead Temp. (10 sec)
-65
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
ORDERING GUIDE MODEL AD9244BST-65,-40 AD9244-EVAL TEMPERATURE RANGE -40C to +85C PACKAGE OPTION ST-48 Evaluation Board
n+2 n+1 n
Analog Input
n+3
n+4 n+5 n+6 n+7 n+8 n+9
clock
data out
n-9
n-8
n-7
n-6
n-5
n-4
n-3
n-2
n-1
n
n+1
Tod = 7nsec typ
Figure 1. AD9244 Input Timing
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9244 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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PRELIMINARY TECHNICAL DATA
AD9244-SPECIFICATIONS
PIN FUNCTION DESCRIPTIONS Pin Nunber Name Descriptions 1,2,5,32,33 AGND Analog Ground 3,4,31,34 AVDD Analog Supply Voltage 5 CLKGND Clock Ground 8,44 NC Do not connect 7,6 CLK+,CLK- Differential Clock Input 9 OEB Digital Output Enable (active low) 10 DB0 (LSB) Least Significant Bit, digital output 11-13,16-21 24-26 DB1 - DB12 Digital outputs 27 DB13 (MSB) Most Significant Bit, digital output 14,22,30 DRGND Digital Ground 15,23,29 DRVDD Digital Supply Voltage 28 OTR Out of range indicator (logic 1 indicates OTR) 35 DFS Data Format Select, connect to; DRGND for straight binary DRVDD for 2's complement 36 REFSENSE Internal reference control 37 VREF Internal Reference 38 REFGND Reference ground 39,40,41,42 REFT,REFB Internal ADC reference decoupling 43 DUTY 50% Duty Cycle Restore, (Connect to AVDD to activate 50% duty cycle restore, decouple to AGND for external control of both clock edges.) 45 CML Common mode reference (0.5*AVDD) 46,47 VIN+,VINDifferential analog inputs 48 VR Internal Bias Decoupling
REFGND
DUTY
REFT
REFT
48 47 46 45 44 43 42 41 40 39 38 37 AGND AGND AVDD AVDD AGND CLKCLK+ NC OEB 1 2 3 4 5 6 7 8 9 36 REF SENSE 35 DFS 34 AVDD 33 AGND
VREF
32 AGND 31 AVDD 30 DRGND 29 DRVDD 28 OTR 27 DB13 (MSB) 26 DB12 25 DB11
REFB DB9
AD9244 48 LQFP (Pr elim inar y and not to scale)
DB0 (LSB) 10 DB1 11 DB2 12 13 14 15 16 17 18 19 20 21 22 23 24
REFB DRGND
VIN+
CML DB4
VIN-
NC DB5
VR DB3
DRGND
DRVDD
DB6
DB7
DB8
DRVDD
DB10
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PRELIMINARY TECHNICAL DATA
AD9244-SPECIFICATIONS
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY (INL) INL refers to the deviation of each individual code from a line drawn from "negative full scale" through "positive full scale." The point used as "negative full scale" occurs 1/2 LSB before the first code transition. "Positive full scale" is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. DIFFERENTIAL NONLINEARITY (DNL, NO MISSING CODES) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 14-bit resolution indicates that all 16384 codes, respectively, must be present over all operating ranges. ZERO ERROR The major carry transition should occur for an analog value 1/2 LSB below VIN+ = VIN-. Zero error is defined as the deviation of the actual transition from that point. GAIN ERROR The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. TEMPERATURE DRIFT The temperature drift for zero error and gain error specifies the maximum change from the initial (+25C) value to the value at TMIN or TMAX. POWER SUPPLY REJECTION The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. APERTURE JITTER The variation in aperture delay for successive samples which is manifested as noise on the input to the A/D. APERTURE DELAY Aperture delay is a measure of the sample-and-hold amplifier (SHA) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion. SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD) RATIO The ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. EFFECTIVE NUMBER OF BITS (ENOB) For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, N = (SINAD - 1.76)/6.02 it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. TOTAL HARMONIC DISTORTION (THD) The ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. SIGNAL-TO-NOISE RATIO (SNR) The ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. SPURIOUS FREE DYNAMIC RANGE (SFDR) The difference in dB between the rms amplitude of the input signal and the peak spurious signal. NYQUIST SAMPLING When the frequency components of the analog input are below the Nyquist frequency (Fclock/2), this is often referred to as Nyquist sampling. IF SAMPLING Due to the effects of aliasing, an ADC is not necessarily limited to Nyquist sampling. Higher sampled frequencies will be aliased down into the 1st Nyquist zone (DCFclock/2) on the output of the ADC. Care must be taken that the bandwidth of the sampled signal does not overlap Nyquist zones and alias onto itself. Nyquist sampling performance is limited by the bandwidth of the input SHA and clock jitter (jitter adds more noise at higher input frequencies).
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TYPICALPERFORMANCECHARACTERISTICS-AD9244
(AVDD = 5.0V, DRVDD = 3.0V, fSAMPL E= 65MSPS with CLK Duty Cycle Stabilizer Enabled, TA =25C, Differential Input Span, , VCM = 2.5V, AIN = -0.5dBFS, VREF = 2.0V, FFT length = 8K, unless otherwise noted)
TPC1. Single Tone 8K FFT, fIN = 5MHz
TPC2. Single Tone SNR/SFDR vs AIN, fIN = 5MHz
TPC3. Single Tone 8K FFT, fIN = 31MHz
TPC4. Dual-Tone SNR/SFDR vs. AIN with fIN1 = 18MHz and fIN2 = 20MHz
TPC5. 3rd Order Intermodulation Distortion vs. Fin1,Fin2 at Ain1,Ain2=-6.5dBFS. Spacing between Fin1 and Fin2 = 1MHz.
TPC6. Single Tone SNR/SFDR vs AIN, fIN = 31MHz
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TYPICALPERFORMANCECHARACTERISTICS-AD9244
(AVDD = 5.0V, DRVDD = 3.0V, fSAMPL E= 65MSPS with CLK Duty Cycle Stabilizer Enabled, TA =25C, Differential Input Span, , VCM = 2.5V, AIN = -0.5dBFS, VREF = 2.0V, FFT length = 8K, unless otherwise noted)
TPC7. SINAD/ENOB vs. Frequency
TPC10. SNR vs. Frequency
TPC8. THD vs. Frequency
TPC11. SFDR vs. Frequency
TPC9. SNR vs. Temperature and Frequency
TPC12. THD vs. Temperature and Frequency
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TYPICALPERFORMANCECHARACTERISTICS-AD9244
(AVDD = 5.0V, DRVDD = 3.0V, fSAMPL E= 65MSPS with CLK Duty Cycle Stabilizer Enabled, TA =25C, Differential Input Span, , VCM = 2.5V, AIN = -0.5dBFS, VREF = 2.0V, FFT length = 8K, unless otherwise noted)
TPC13. Harmonics vs. Frequency
TPC16. SINAD vs. Sample Rate
TPC14. SFDR vs. Sample Rate
TPC17. SINAD/SFDR vs. Duty Cycle, , fIN = 20MHz
TPC15. Typical INL
TPC18. Typical DNL -10-
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TYPICALPERFORMANCECHARACTERISTICS-AD9244
(AVDD = 5.0V, DRVDD = 3.0V, fSAMPL E= 65MSPS with CLK Duty Cycle Stabilizer Enabled, TA =25C, Differential Input Span, , VCM = 2.5V, AIN = -0.5dBFS, VREF = 2.0V, FFT length = 8K, unless otherwise noted)
TPC19. Dual-Tone 8K FFT, fIN1 = 44.2MHz and fIN2 = 45.6MHz
TPC22. Dual Tone SNR and SFDR, fIN1 = 44.2MHz and fIN2 = 45.6MHz
TPC20. Dual-Tone 8K FFT, fIN1 = 69.2MHz and fIN2 = 70.6MHz
TPC23. Dual-Tone SNR and SFDR, fIN1 = 69.2MHz and fIN2 = 70.6MHz
TPC21. Dual-Tone 8K FFT, fIN1 = 139.2MHz and fIN2 = 140.7MHz
TPC24. Dual-Tone SNR and SFDR, fIN1 = 139.2MHz and fIN2 = 140.7MHz -11-
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TYPICALPERFORMANCECHARACTERISTICS-AD9244
(AVDD = 5.0V, DRVDD = 3.0V, fSAMPL E= 65MSPS with CLK Duty Cycle Stabilizer Enabled, TA =25C, Differential Input Span, , VCM = 2.5V, AIN = -0.5dBFS, VREF = 2.0V, FFT length = 8K, unless otherwise noted)
TPC25. Single Tone 8K FFT at IF = 190.82MHz (typical WCDMA carrier), fSAMPLE = 61.44MSPS
TPC28. Single Tone SNR and SFDR at IF = 190.82 MHz (typical WCDMA carrier), fSAMPLE = 61.44MSPS
TPC26. Dual-Tone 8K FFT, fIN1 = 239.1MHz and fIN2 = 240.7MHz
TPC29. Dual-Tone SNR and SFDR, fIN1 = 239.1MHz and fIN2 = 240.7MHz
TPC27. CMRR vs. Frequency (AIN = 0dBFS and CML = 2.5V
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TYPICALPERFORMANCECHARACTERISTICS-AD9244
AD9244 - SINAD/SFDR vs. AIN at FIN=190 MHz
95 90
85
dBFS and dBc
80 SINAD-dBc 75 SINAD-dBFS SFDR-dBc SFDR-dBFS 70
65
60
55 -24 -19 -14 -9 -4 1
AIN-dBFS
TPC30. Undersampling Performance of AD9244, fCLK=65MSPS, Driving ADC Inputs with Transformer and Balun
AD9244 - SNR/SFDR vs. AIN at FIN=240 MHz
100
90
80
dBFS and dBc
SNR-dBc SNR-dBFS 70 SFDR-dBc SFDR-dBFS
60
50
40 -24 -19 -14 -9 -4 1
AIN-dBFS
TPC31. Undersampling Performance of AD9244, fCLK=65MSPS, Driving ADC Inputs with Transformer and Balun
AD9244 with FIN= 240 MHz and FCLK=65 MSPS (2 V Input Span-Differential, Ain=-8.5 dBFS)
0 -10 -20 -30 -40 -50
Note: Spur Floor Below 90 dBc @ 240 MHz! SNR=73 dBFS THD=-89.5 dBFS SINAD=72.7 dBFS
dBFs
-60 -70 -80 -90 -100 -110 -120 0 4 8 12 16 20 24 28 32
Frequency (MHz)
TPC32. Undersampling Performance of AD9244, Driving ADC Inputs with Transformer and Balun
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PRELIMINARY TECHNICAL DATA
AD9244
THEORY OF OPERATION
The AD9244 is a high performance, single supply 14-bit ADC. In addition to high dynamic range Nyquist sampling, it is designed for excellent IF undersampling performance with an input analog bandwidth of 750MHz. The AD9244 utilizes an eight stage pipeline architecture with a wideband, calibrated, input sample and hold amplifier (SHA) implemented on a cost-effective CMOS process. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC along with a switched capacitor DAC and interstage residue amplifier (MDAC). The MDAC amplifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The performance of the AD9244 is greatly enhanced by the use of active calibration, yielding superb dynamic performance. The pipeline architecture allows a greater throughput rate at the expense of pipeline delay or latency. While the converter captures a new input sample every clock cycle, it takes eight clock cycles for the conversion to be fully processed and appear at the output. This is illustrated in Figure 1 on page 5. This latency is not a concern in many applications. The digital output, together with the out-ofrange indicator (OTR), is latched into an output buffer to drive the output pins. The output drivers of the AD9244 can be configured to interface with +5V or +3V logic families. Connecting the DUTY pin to AVDD implements the internal clock stabilization function in the AD9244. In this mode, the AD9244 generates its own internal falling edge to create an internal 50% duty cycle clock, independent of the externally applied duty cycle. See the pin function descriptions on page 6 for details. If the DUTY pin is connected to ground through a 10K resistor or left floating (and decoupled), the AD9244 will use both edges of the external clock in its internal timing circuitry (see Figure 1 and specification page for exact timing requirements). Control of straight binary or two's complement output format is accomplished with the DFS pin. See the pin function descriptions on page 6 for details. The ADC samples the analog input on the rising edge of the clock. While clock is low, the input SHA is in sample mode. When the clock transitions to a high logic level, the SHA goes into the hold mode. System disturbances just prior to or immediately after the rising edge of the clock and/or excessive clock jitter may cause the input SHA to acquire the wrong value, and should be minimized. ANALOG INPUT OPERATION Figure 2 shows the equivalent analog input of the AD9244 which consists of a 750 MHz differential SHA. The differential input structure of the SHA is flexible, allowing the device to be configured for either a differential or single-ended input. The analog inputs VIN+ and VINare interchangeable, with the exception that reversing the
REV. PrD 01/22/02
inputs to the VIN+ and VIN- pins results in a data inversion (complementing the output word).
S
CH S CS VIN+ CPIN,PAR VINCPIN,PAR
S H CS
+
CH
S
Figure 2. Analog Input of AD9244 SHA The optimum noise and dc linearity performance for either differential or single-ended inputs is achieved with the largest input signal voltage span (i.e., 2V input span) and matched input impedance for VIN+ and VIN-. Only a slight degradation in dc linearity performance exists between the 2V and 1V input spans. High frequency inputs may find the 1V span better suited to achieve superior SFDR performance. (See Typical Performance Characteristics.) When the ADC is driven by an op amp and a capacitive load is switched onto the output of the op amp, the output will momentarily drop due to its effective output impedance. As the output recovers, ringing may occur. To remedy the situation, a series resistor can be inserted between the op amp and the SHA input as shown in Figure 3. A shunt capacitance also acts like a charge reservoir, sinking or sourcing the additional charge required by the hold capacitor, CH, further reducing current transients seen at the op amp's output.
VCC RS 33 RS 33 VEE 15pF VINVREF
AD9244
VIN+
10F
0.1F
REFSENSE REFCOM
Figure 3. Resistors Isolating SHA Input from Op Amp The optimum size of this resistor is dependent on several factors, including the ADC sampling rate, the selected op amp, and the particular application. In most applications, a 30 to 100 resistor is sufficient.
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PRELIMINARY TECHNICAL DATA
AD9244
For noise sensitive applications, the very high bandwidth of the AD9244 may be detrimental and the addition of a series resistor and/or shunt capacitor can help limit the wideband noise at the ADC's input by forming a low pass filter. The source impedance driving VIN+ and VINshould be matched. Failure to provide matching may result in degradation of the SNR, THD, or SFDR of the AD9244. ANALOG INPUT AND REFERENCE OVERVIEW The differential input span of the AD9244 is equal to the potential at the VREF pin. The VREF potential may be obtained from the internal AD9244 reference or an external source. In differential applications, the center point of the input span is obtained by the common mode level of the signals. In single ended applications, the center point is the dc potential applied to one input pin while the signal is applied to the opposite input pin. Figure 4 is a simplified model of the AD9244 analog input, showing the relationship between the analog inputs, VIN+, VIN-, and the reference voltage, VREF. Note that this is only a symbolic model and that no actual negative voltages exist inside the AD9244. Similar to the voltages applied to the top and bottom of the resistor ladder in a flash ADC, the value VREF/2 defines the minimum and maximum input voltages to the ADC core. Figure 4. Equivalent Analog Input of AD9244 The addition of a differential input structure allows the user to easily configure the inputs for either single-ended or differential operation. The ADC's input structure allows the dc offset of the input signal to be varied independently of the input span of the converter. Specifically, the input to the ADC core can be defined as the difference of the voltages applied at the VIN+ and VIN- input pins. Therefore, the equation VCORE = VIN+ - VIN(1) defines the output of the differential input stage and provides the input to the ADC core. The voltage, VCORE, must satisfy the condition, -VREF/2 < VCORE < VREF/2 where VREF is the voltage at the VREF pin. (2)
VIN+ + VIN-
AD9244
+VREF/2 ADC CORE -VREF/2 14
VCORE
Table I. Analog Input Configuration Summary
Input Connection Single-Ended Coupling Input Span (V) Input Range (V) VIN+ 1 VIN- 1 0.5 to 1.5 1 to 3 1.0 2.0 Comments Best for stepped input response applications, requires 5 V op amp. Optimum noise performance for single ended mode, often requires low distortion op amp with VCC > +5 V due to its headroom issues. Optimum full-scale THD and SFDR performance well beyond the ADC's Nyquist frequency. Preferred mode for undersampling applications. Optimum noise performance for differential mode.
DC or AC 1.0 2.0
Differential DC or AC 1.0 (via Transformer) or Amplifier 2.0
2.25 to 2.75
2.75 to 2.25
2.0 to 3.0
3.0 to 2.0
NOTE 1 VIN+ and VIN- can be interchanged if signal inversion is required.
Table II. Reference Configuration Summary
Reference Operating Mode INTERNAL INTERNAL INTERNAL EXTERNAL
Input Span (VIN+-VIN-) (V p-p) 1 2 1 SPAN 2 (SPAN=VREF) SPAN=EXTERNAL REF
Required VREF (V) 1 2 1 VREF 2.0 VREF = (1 + R1/R2) 1 VREF 2.0
Connect REFSENSE REFSENSE R1 R2 REFSENSE VREF
To VREF AGND VREF AND REFSENSE
REFSENSE AND REFGND
AVDD EXTERNAL REF
REV. PrD 01/22/02
-15-
PRELIMINARY TECHNICAL DATA
AD9244
In addition to the limitations placed on the input voltages VIN+ and VIN- by Equation 2, boundaries on the inputs also exist based on the power supply voltages according to the conditions AGND - 0.3V < VIN+ < AVDD + 0.3V AGND - 0.3V < VIN- < AVDD + 0.3V where AGND is nominally 0V and AVDD is nominally +5 V. The range of valid inputs for VIN+ and VIN- is any combination that satisfies both Equations 2 and 3.
1V
AD9244
TO ADC REFT 2.5V A2 REFB
(3)
VREF A1
For additional information showing the relationship between VIN+, VIN-, VREF and the analog input range of the AD9244, see Tables I and II on page 15. REFERENCE OPERATION The AD9244 contains a bandgap reference which provides a pin-strappable option to generate either a 1V or 2V output. With the addition of two external resistors, the user can generate reference voltages between 1V and 2V. Another alternative is to use an external reference for designs requiring enhanced accuracy and/or drift performance as described later in this section. Figure 5a shows a simplified model of the internal voltage reference of the AD9244. A reference amplifier buffers a 1V fixed reference. The output from the reference amplifier, A1, appears on the VREF pin. As stated earlier, the voltage on the VREF pin determines the full scale differential input span of the ADC. The voltage appearing at the VREF pin, and the state of the internal reference amplifier, A1, are determined by the voltage present at the REFSENSE pin. The logic circuitry contains comparators that monitor the voltage at the REFSENSE pin. If REFSENSE is tied to AGND, the switch is connected to the internal resistor network thus providing a VREF of 2.0V. If REFSENSE is tied to VREF pin via a short or resistor, the switch will connect to the REFSENSE pin. This connection will provide a VREF of 1.0V. An external resistor network will provide an alternative VREF between 1.0V and 2.0V (see Figure 6). Another comparator controls internal circuitry which disables the reference amplifier if REFSENSE is tied to AVDD. Disabling the reference amplifier allows the VREF pin to be driven by an external voltage reference. The actual reference voltages used by the internal circuitry of the AD9244 appear on the REFT and REFB pins. The voltages on these pins are symmetrical about the analog supply. For proper operation when using an internal or external reference, it is necessary to add a capacitor network to decouple these pins. Figure 5b shows the recommended decoupling network. The turn-on time of the reference voltage appearing between REFT and REFB is approximately 10ms and should be evaluated in any power down mode of operation. USING THE INTERNAL REFERENCE The AD9244 can be easily configured for either a 1V p-p differential input span or 2V p-p input span by setting the internal reference. Other input spans can be realized with two external gain-setting resistors as shown in Figure 6 of this data sheet, or using an external reference.
REV. PrD 01/22/02
REFSENSE DISABLE LOGIC A1 REFGND
Figure 5a. AD9244 Equivalent Reference Circuit
0.1F VREF 10F 0.1F REFT 0.1F 10F
AD9244
REFB
0.1F
Figure 5b. REFT and REFB Decoupling Pin Programmable Reference By shorting the VREF pin directly to the REFSENSE pin, the internal reference amplifier is placed in a unity gain mode and the resultant VREF output is 1V. By shorting the REFSENSE pin directly to the REFGND pin, the internal reference amplifier is configured for a gain of 2.0 and the resultant VREF output is 2.0V. The VREF pin should be bypassed to the REFGND pin with a 10F tantalum capacitor in parallel with a low-inductance 0.1F ceramic capacitor as shown in Figure 6. Resistor Programmable Reference Figure 6 shows an example of how to generate a reference voltage other than 1.0V or 2.0V with the addition of two external resistors. Use the equation, VREF = 1V x(1 + R1/R2) to determine appropriate values for R1 and R2. These resistors should be in the 2K to 10K range. For the example shown, R1 equals 2.5K and R2 equals 5K. From the equation above, the resultant reference voltage on the VREF pin is 1.5 V. This sets the differential input span to be 1.5V p-p. The midscale voltage can also be set to VREF by connecting VIN- to VREF.
3.25V 1.75V 2.5V 33 1.5V 10F 0.1F R1 2.5K R2 5K 33 15pF VINREFT VREF REFSENSE REFB REFGND 0.1F 0.1F 10F
AD9244
VIN+ 0.1F
Figure 6. Resistor Programmable Reference (1.5V p-p Input Span, Differential Input with VCM = 2.5V -16-
PRELIMINARY TECHNICAL DATA
AD9244
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48 pin LQFP package (ST-48)
0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45) SEATING 0.006 (0.15) PLANE 0.002 (0.05) 0.057 (1.45) 0.053 (1.35)
48 1
0.354 (9.00) BSC 0.276 (7.0) BSC
37 36
TOP VIEW
(PINS DOWN)
0.276 0.354 (7.0) (9.00) BSC BSC
COPLANARITY (0.08) 0 MIN 0 - 7 0.007 (0.2) 0.004 (0.09)
12 13
25 24
0.019 (0.5) BSC
0.011 (0.27) 0.006 (0.17)
REV. PrD 01/22/02
17

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